DirLabel =/net/plato.ee.Virginia.EDU/users/bengroup/workspace/alicia/tutorials/cadence 
Target Library =scan_chain 
Reference Libraries =yq_IBM130LPVT 
Verilog Design Files =/net/plato.ee.Virginia.EDU/users/bengroup/workspace/alicia/tutorials/blockSynthesis/enc/scan_chain/scan_chain_PLACED.v  
-y Options = 
Library Extn. = 
-v Options = 
-f Options = 
Ignore Modules File = 
Import Modules File = 
Log File =./verilogIn.log 
Work Area =/tmp 
Power Net =power 
Ground Net =ground 
Global Signals = 
Net Expression Property Name for Power Net =vdd 
Net Expression Property Name for Ground Net =gnd 
Create Net Expression =false
Connect By Name Nets = 
Import Modules That Match Existing Target Library Cells =true
Verilog Cell Modules =Create Symbol Only
Verilog Structural Modules View =schematic
Functional View Name =functional 
Netlist View Name =netlist 
Schematic View Name =schematic 
Symbol View Name =symbol 
Name Map Table = ./verilogIn.map.table 
Overwrite Symbol Views =None
Sheet Size =none
Pin Placement Flag =Left and Right Sides
Pin Placement File = 
Label Size =0.062500 
Maximum Number Of Rows =1024 
Maximum Number of Columns =1024 
Line-Line Spacing =   0.20000 
Line-Component Spacing =   0.50000 
Density Level =0 
Full Place and Route =false
Fast labels =false
Minimize Cross Over =false
Generate Square Schematics =true
Extract Schematics =true
Ignore Extra Pins =false
No Dummy Nets In Netlist View =false
Verbose =true
Generate Snap Space Properties =true
Through CellView Library =basic 
Through CellView Cell =cds_thru 
Through CellView View =symbol 
Continuous Assignment CellView Library =basic 
Continuous Assignment CellView Cell =patch 
Continuous Assignment CellView View =symbol 
Pre Compiled Library = 
Destination IR Lib = 
ViewName for IR Library =hdl 
Only Compile a Verilog Library =false
Text to Symbol Generator Files = 
